module AXI4RAM(
  input         clock,
  input         reset,
  output        io_in_awready,
  input         io_in_awvalid,
  input  [31:0] io_in_awaddr,
  output        io_in_wready,
  input         io_in_wvalid,
  input  [63:0] io_in_wdata,
  input  [7:0]  io_in_wstrb,
  input         io_in_wlast,
  output        io_in_bvalid,
  output        io_in_arready,
  input         io_in_arvalid,
  input  [31:0] io_in_araddr,
  input  [7:0]  io_in_arlen,
  input  [2:0]  io_in_arsize,
  input  [1:0]  io_in_arburst,
  output        io_in_rvalid,
  output [63:0] io_in_rdata,
  output        io_in_rlast
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [63:0] _RAND_12;
`endif // RANDOMIZE_REG_INIT
  wire  RAMHelper_clk; // @[AXI4RAM.scala 52:21]
  wire [63:0] RAMHelper_rIdx; // @[AXI4RAM.scala 52:21]
  wire [63:0] RAMHelper_rdata; // @[AXI4RAM.scala 52:21]
  wire [63:0] RAMHelper_wIdx; // @[AXI4RAM.scala 52:21]
  wire [63:0] RAMHelper_wdata; // @[AXI4RAM.scala 52:21]
  wire [63:0] RAMHelper_wmask; // @[AXI4RAM.scala 52:21]
  wire  RAMHelper_wen; // @[AXI4RAM.scala 52:21]
  wire [7:0] _T_9 = io_in_wstrb[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_11 = io_in_wstrb[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_13 = io_in_wstrb[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_15 = io_in_wstrb[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_17 = io_in_wstrb[4] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_19 = io_in_wstrb[5] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_21 = io_in_wstrb[6] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [7:0] _T_23 = io_in_wstrb[7] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12]
  wire [31:0] _T_26 = {_T_15,_T_13,_T_11,_T_9}; // @[Cat.scala 29:58]
  wire [31:0] _T_29 = {_T_23,_T_21,_T_19,_T_17}; // @[Cat.scala 29:58]
  reg [7:0] value; // @[Counter.scala 29:33]
  reg [7:0] value_1; // @[Counter.scala 29:33]
  wire  _T_30 = io_in_arready & io_in_arvalid; // @[Decoupled.scala 40:37]
  reg [7:0] _T_32; // @[Reg.scala 27:20]
  wire [7:0] _GEN_0 = _T_30 ? io_in_arlen : _T_32; // @[Reg.scala 28:19]
  reg [1:0] _T_36; // @[Reg.scala 27:20]
  wire [1:0] _GEN_1 = _T_30 ? io_in_arburst : _T_36; // @[Reg.scala 28:19]
  wire [31:0] _T_38 = {{24'd0}, io_in_arlen}; // @[AXI4Slave.scala 45:69 AXI4Slave.scala 45:69]
  wire [38:0] _GEN_24 = {{7'd0}, _T_38}; // @[AXI4Slave.scala 45:89]
  wire [38:0] _T_39 = _GEN_24 << io_in_arsize; // @[AXI4Slave.scala 45:89]
  wire [38:0] _T_40 = ~_T_39; // @[AXI4Slave.scala 45:42]
  wire [38:0] _GEN_25 = {{7'd0}, io_in_araddr}; // @[AXI4Slave.scala 45:40]
  wire [38:0] _T_41 = _GEN_25 & _T_40; // @[AXI4Slave.scala 45:40]
  reg [38:0] _T_44; // @[Reg.scala 27:20]
  wire [38:0] _GEN_2 = _T_30 ? _T_41 : _T_44; // @[Reg.scala 28:19]
  wire [7:0] _T_49 = value_1 + 8'h1; // @[Counter.scala 39:22]
  wire  _T_50 = _GEN_1 == 2'h2; // @[AXI4Slave.scala 50:21]
  wire  _T_51 = value_1 == _GEN_0; // @[AXI4Slave.scala 50:68]
  wire  _T_52 = _T_50 & _T_51; // @[AXI4Slave.scala 50:51]
  wire [7:0] _GEN_3 = _T_52 ? 8'h0 : _T_49; // @[AXI4Slave.scala 50:77]
  reg  _T_79; // @[AXI4Slave.scala 73:17]
  wire  _T_81 = ~io_in_rlast; // @[AXI4Slave.scala 73:65]
  wire  _T_82 = io_in_rvalid & _T_81; // @[AXI4Slave.scala 73:62]
  wire  ren = _T_79 | _T_82; // @[AXI4Slave.scala 73:46]
  wire [7:0] _GEN_4 = ren ? _GEN_3 : value_1; // @[AXI4Slave.scala 48:18]
  wire [7:0] _T_56 = value + 8'h1; // @[Counter.scala 39:22]
  wire [31:0] _T_58 = io_in_araddr >> io_in_arsize; // @[AXI4Slave.scala 57:45]
  wire [31:0] _T_59 = _T_58 & _T_38; // @[AXI4Slave.scala 57:67]
  wire  _T_60 = io_in_arlen != 8'h0; // @[AXI4Slave.scala 58:32]
  wire  _T_61 = io_in_arburst == 2'h2; // @[AXI4Slave.scala 58:62]
  wire  _T_62 = _T_60 & _T_61; // @[AXI4Slave.scala 58:40]
  wire  _T_63 = io_in_arlen == 8'h1; // @[AXI4Slave.scala 59:35]
  wire  _T_64 = io_in_arlen == 8'h3; // @[AXI4Slave.scala 59:63]
  wire  _T_65 = _T_63 | _T_64; // @[AXI4Slave.scala 59:43]
  wire  _T_66 = io_in_arlen == 8'h7; // @[AXI4Slave.scala 60:30]
  wire  _T_67 = _T_65 | _T_66; // @[AXI4Slave.scala 59:71]
  wire  _T_68 = io_in_arlen == 8'hf; // @[AXI4Slave.scala 60:58]
  wire  _T_69 = _T_67 | _T_68; // @[AXI4Slave.scala 60:38]
  wire  _T_71 = _T_69 | reset; // @[AXI4Slave.scala 59:17]
  wire  _T_72 = ~_T_71; // @[AXI4Slave.scala 59:17]
  wire [31:0] _GEN_7 = _T_30 ? _T_59 : {{24'd0}, _GEN_4}; // @[AXI4Slave.scala 56:29]
  wire  _T_75 = io_in_rvalid & io_in_rlast; // @[AXI4Slave.scala 70:56]
  reg  r_busy; // @[StopWatch.scala 24:20]
  wire  _GEN_8 = _T_75 ? 1'h0 : r_busy; // @[StopWatch.scala 26:19]
  wire  _GEN_9 = _T_30 | _GEN_8; // @[StopWatch.scala 27:20]
  wire  _T_85 = _T_30 | r_busy; // @[AXI4Slave.scala 74:52]
  wire  _T_86 = ren & _T_85; // @[AXI4Slave.scala 74:35]
  reg  _T_88; // @[StopWatch.scala 24:20]
  wire  _GEN_10 = io_in_rvalid ? 1'h0 : _T_88; // @[StopWatch.scala 26:19]
  wire  _GEN_11 = _T_86 | _GEN_10; // @[StopWatch.scala 27:20]
  reg [7:0] value_2; // @[Counter.scala 29:33]
  wire  _T_89 = io_in_awready & io_in_awvalid; // @[Decoupled.scala 40:37]
  reg [31:0] _T_91; // @[Reg.scala 27:20]
  wire [31:0] _GEN_12 = _T_89 ? io_in_awaddr : _T_91; // @[Reg.scala 28:19]
  wire  _T_93 = io_in_wready & io_in_wvalid; // @[Decoupled.scala 40:37]
  wire [7:0] _T_96 = value_2 + 8'h1; // @[Counter.scala 39:22]
  reg  w_busy; // @[StopWatch.scala 24:20]
  wire  _GEN_15 = io_in_bvalid ? 1'h0 : w_busy; // @[StopWatch.scala 26:19]
  wire  _GEN_16 = _T_89 | _GEN_15; // @[StopWatch.scala 27:20]
  wire  _T_102 = _T_93 & io_in_wlast; // @[AXI4Slave.scala 97:43]
  reg  _T_104; // @[StopWatch.scala 24:20]
  wire  _GEN_17 = io_in_bvalid ? 1'h0 : _T_104; // @[StopWatch.scala 26:19]
  wire  _GEN_18 = _T_102 | _GEN_17; // @[StopWatch.scala 27:20]
  wire [31:0] _T_113 = _GEN_12 & 32'h7ffffff; // @[AXI4RAM.scala 44:33]
  wire [28:0] _GEN_27 = {{21'd0}, value_2}; // @[AXI4RAM.scala 47:27]
  wire [28:0] wIdx = _T_113[31:3] + _GEN_27; // @[AXI4RAM.scala 47:27]
  wire [38:0] _T_116 = _GEN_2 & 39'h7ffffff; // @[AXI4RAM.scala 44:33]
  wire [35:0] _GEN_28 = {{28'd0}, value_1}; // @[AXI4RAM.scala 48:27]
  wire [35:0] rIdx = _T_116[38:3] + _GEN_28; // @[AXI4RAM.scala 48:27]
  wire  _T_120 = wIdx < 29'h1000000; // @[AXI4RAM.scala 45:32]
  reg [63:0] _T_121; // @[Reg.scala 15:16]
  wire  _GEN_31 = _T_30 & _T_62; // @[AXI4Slave.scala 59:17]
  RAMHelper RAMHelper ( // @[AXI4RAM.scala 52:21]
    .clk(RAMHelper_clk),
    .rIdx(RAMHelper_rIdx),
    .rdata(RAMHelper_rdata),
    .wIdx(RAMHelper_wIdx),
    .wdata(RAMHelper_wdata),
    .wmask(RAMHelper_wmask),
    .wen(RAMHelper_wen)
  );
  assign io_in_awready = ~w_busy; // @[AXI4Slave.scala 94:15]
  assign io_in_wready = io_in_awvalid | w_busy; // @[AXI4Slave.scala 95:15]
  assign io_in_bvalid = _T_104; // @[AXI4Slave.scala 97:14]
  assign io_in_arready = 1'h1; // @[AXI4Slave.scala 71:15]
  assign io_in_rvalid = _T_88; // @[AXI4Slave.scala 74:14]
  assign io_in_rdata = _T_121; // @[AXI4RAM.scala 69:18]
  assign io_in_rlast = value == _GEN_0; // @[AXI4Slave.scala 47:24]
  assign RAMHelper_clk = clock; // @[AXI4RAM.scala 53:16]
  assign RAMHelper_rIdx = {{28'd0}, rIdx}; // @[AXI4RAM.scala 54:17]
  assign RAMHelper_wIdx = {{35'd0}, wIdx}; // @[AXI4RAM.scala 55:17]
  assign RAMHelper_wdata = io_in_wdata; // @[AXI4RAM.scala 56:18]
  assign RAMHelper_wmask = {_T_29,_T_26}; // @[AXI4RAM.scala 57:18]
  assign RAMHelper_wen = _T_93 & _T_120; // @[AXI4RAM.scala 58:16]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  value = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  value_1 = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  _T_32 = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  _T_36 = _RAND_3[1:0];
  _RAND_4 = {2{`RANDOM}};
  _T_44 = _RAND_4[38:0];
  _RAND_5 = {1{`RANDOM}};
  _T_79 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  r_busy = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  _T_88 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  value_2 = _RAND_8[7:0];
  _RAND_9 = {1{`RANDOM}};
  _T_91 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  w_busy = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  _T_104 = _RAND_11[0:0];
  _RAND_12 = {2{`RANDOM}};
  _T_121 = _RAND_12[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
  always @(posedge clock) begin
    if (reset) begin
      value <= 8'h0;
    end else if (io_in_rvalid) begin
      if (io_in_rlast) begin
        value <= 8'h0;
      end else begin
        value <= _T_56;
      end
    end
    if (reset) begin
      value_1 <= 8'h0;
    end else begin
      value_1 <= _GEN_7[7:0];
    end
    if (reset) begin
      _T_32 <= 8'h0;
    end else if (_T_30) begin
      _T_32 <= io_in_arlen;
    end
    if (reset) begin
      _T_36 <= 2'h0;
    end else if (_T_30) begin
      _T_36 <= io_in_arburst;
    end
    if (reset) begin
      _T_44 <= 39'h0;
    end else if (_T_30) begin
      _T_44 <= _T_41;
    end
    if (reset) begin
      _T_79 <= 1'h0;
    end else begin
      _T_79 <= _T_30;
    end
    if (reset) begin
      r_busy <= 1'h0;
    end else begin
      r_busy <= _GEN_9;
    end
    if (reset) begin
      _T_88 <= 1'h0;
    end else begin
      _T_88 <= _GEN_11;
    end
    if (reset) begin
      value_2 <= 8'h0;
    end else if (_T_93) begin
      if (io_in_wlast) begin
        value_2 <= 8'h0;
      end else begin
        value_2 <= _T_96;
      end
    end
    if (reset) begin
      _T_91 <= 32'h0;
    end else if (_T_89) begin
      _T_91 <= io_in_awaddr;
    end
    if (reset) begin
      w_busy <= 1'h0;
    end else begin
      w_busy <= _GEN_16;
    end
    if (reset) begin
      _T_104 <= 1'h0;
    end else begin
      _T_104 <= _GEN_18;
    end
    if (ren) begin
      _T_121 <= RAMHelper_rdata;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_31 & _T_72) begin
          $fwrite(32'h80000002,"Assertion failed\n    at AXI4Slave.scala:59 assert(axi4.ar.bits.len === 1.U || axi4.ar.bits.len === 3.U ||\n"); // @[AXI4Slave.scala 59:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_31 & _T_72) begin
          $fatal; // @[AXI4Slave.scala 59:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule


/*--------------------------------------------*/

`define RAMWIDTH 64
import "DPI-C" function void ram_helper
(
  input  longint    rIdx,
  output longint    rdata,
  input  longint    wIdx,
  input  longint    wdata,
  input  longint    wmask,
  input  bit    wen
);

module RAMHelper(
  input         clk,
  input  [`RAMWIDTH-1:0] rIdx,
  output [`RAMWIDTH-1:0] rdata,
  input  [`RAMWIDTH-1:0] wIdx,
  input  [`RAMWIDTH-1:0] wdata,
  input  [`RAMWIDTH-1:0] wmask,
  input         wen
);

  always @(posedge clk) begin
    ram_helper(rIdx, rdata, wIdx, wdata, wmask, wen);
  end
  //assign rdata = ram[rIdx];
  //assign ram[wIdx] = wen?(ram[wIdx] &~wmask) | (wdata & wmask):0;
endmodule

